High-speed digital data links may suffer from inter-symbol interference, especially in situations in which loss, reflections or other imperfections exist in the transmission channel. Inter-symbol interference may have the effect that the signal received during a given clock cycle is a linear combination of the bit transmitted during the corresponding clock cycle at the transmitter, and of the bits transmitted during a number of preceding clock cycles. The effects of inter-symbol interference may be mitigated using a technique referred to as decision feedback equalization (DFE) which involves correcting the received signal at the sampling point, during each clock cycle, with a linear combination of the bits received during a number of preceding clock cycles.
The contribution from the immediately preceding received bit, which is referred to as the first tap, may be generated using a technique referred to as predictive decision feedback equalization (predictive DFE, which may also be referred to as speculative DFE or loop-unrolled DFE), in which two correction terms are calculated, one corresponding to a received 1, and one corresponding to a received 0 in the immediately preceding received bit; the appropriate one of these two correction terms is then selected using a multiplexer (MUX) once a binary value for the bit received on the immediately preceding clock cycle is available.
In particular, a current digital to analog converter (DAC) may be used to add a current to the output current of a comparator, which may be implemented as a differential pair, within a clocked comparator used to sample the received signal. The current added to the output effectively implements the preceding bit with the right scaling factor. This approach has several disadvantages. A DAC consumes power and, because it represents a capacitive load, it limits the speed of the circuit.
Thus, there is a need for a system for predictive feedback equalization that achieves improved speed, with acceptable power consumption.